1. Field of the Invention
The present invention relates in general to the process of macro block addresses (MBAs) for expanding a compressed video signal as in a HDTV, and more particularly to a macro block address processor for a digital compressed video signal decoder which is capable of processing macro block addresses successively and stably.
2. Description of the Prior Art
FIG. 1A, FIG. 1B and FIG. 1C illustrate a general relationship among data blocks, macro blocks and slices in encoding/decoding a digital video signal. As shown in this drawing, the digital compressed or encoded video signal is partitioned into the data blocks.fwdarw.the macro blocks.fwdarw.the slices. Each macro block is composed of a fixed number of data blocks and is coded into coefficient data. A macro block address is sent to indicate a position of each macro block. The macro block addresses skip over the macro blocks to which no data is to be transmitted and are sent as relative position data to indicate the macro blocks to which data are to be transmitted practically, thereby to make the efficiency of the signal compression higher. In such a system that expands the digital compressed video signal to restore it to its original state, the process of all macro blocks is performed using the relative macro block addresses, as shown in FIG., 2.
FIG. 2 is a block diagram of a conventional macro block address processor for a digital compressed video signal decoder. As shown in this drawing, the conventional macro block address processor comprises a multiplexer 10 for selecting one of a zero run value for each macro block coefficient data and a zero run value from a zero setter 11 and one of a level value for each macro block coefficient data and a level value from the zero setter 11 in response to a select signal. A down-counter 14 is adapted to count relative macro block addresses and output the counted values as the select signals to the multiplexer 10. A first-in first-out (FIFO) RAM 12 is provided to sequentially store the run values selected by the multiplexer 10 and output them to a coefficient generator (not shown) in the stored order. A FIFO RAM 13 is provided to sequentially store the level values selected by the multiplexer 10 and output them to the coefficient generator in the stored order.
In operation, under the condition that the down-counter 14 counts the macro block addresses and outputs the counted values as the select signals to the multiplexer 10, the zero run value for each macro block coefficient data is selected by the multiplexer 10 and then stored in the FIFO RAM 12 and the level value for each macro block coefficient data is selected by the multiplexer 10 and then stored in the FIFO RAM 13. The FIFO RAMs 12 and 13 then output the stored values to the coefficient generator.
On the other hand, when the down-counter 14 counts the coefficient data for omitted macro blocks as a result of counting the relative macro block addresses, the zero run values from the zero setter 11 are selected by the multiplexer 10 and then stored in the FIFO RAM 12 and the level values from the zero setter 11 are selected by the multiplexer 10 and then stored in the FIFO RAM 13. The FIFO RAMs 12 and 13 then output the stored values to the coefficient generator. The output of the down-counter 14 is also applied as a hold signal to the preceding processing section. The hold signal from the down-counter 14 causes the preceding processing operation to be stopped. As the preceding processing operation is stopped, "O" is produced as the coefficient data for the omitted macro blocks. This means that only the required macro block data must be inputted successively in the signal compression, while all macro block data must be produced in the signal expansion.
However, the conventional macro block address processor has a disadvantage, in that it is not easy to control stopping the preceding processing operation while producing the data for the omitted macro blocks. Also, the control may result in an unstable operation of the macro block address processor.